1. Field of the Invention
The present invention relates to phase-locked loops (PLLs), and in particular relates to injection-locked phase-locked loops (ILPLLs).
2. Description of the Related Art
In modern analog front end designs, there is an increasing demand for high performance analog-to-digital converters, which require a high sampling frequency and a low jitter clock. Thus, phase-locked loops (PLLs) with jitter in the order of a few picoseconds have become a desirable choice.
To get better phase noise, a wider loop bandwidth is needed to suppress the noise of voltage-controlled oscillators (VCOs) of the PLLs. For a wider loop bandwidth of a PLL, an injection-locked technique is introduced in the VCO design of the PLL. However, improper injection timing may cause destructive disturbance. Thus, an injection timing alignment technique is called for.